It delivers very low latency since it is a full hardware host NVMe implementation. That takes only few
dozens of clock cycles (compared to multiple thousands of clock cycles for a software NVMe driver on a
CPU). In addition, there is no needs of PCIe interrupt management because it is directly processed by
the Host NVMe manager, therefore avoiding context switches.
The NVMe Host IP is available for evaluation and demo using a reference design based on a Xilinx
Ultrascale FPGA board attached to a Samsung M.2 NVMe SSD. It embeds a testbench allowing to
configure the IO access : IO size, random/sequential, read/write…
Performance results: it reaches up to 3,4GB/s, which is the limitation of the SSD used (Gen3x4 NVMe
SSD specification max = 3,4GB/s).