Easy NVMe HOST
High Performance Embedded Host NVMe
Host NVM Express
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Overview
- Ultra low latency
- Very high throughput
- Low power architecture
- Low gate count
- No need of CPU
- Easy integration
- Ease of use
- NVM Express Compliant
- Automatic PCIe/NVMe init
- Up to PCIe Gen 3x8
- IO read/write and shutdown commands
- FIFO or AXI4 or Avalon interface
- 128 or 256 bits data path
Deliverables
- Verilog RTL source code
- Low level firmware
- Synthesis scripts
- Technical documentation
- Technical support
Description
The architecture of the Host NVM Express IP is based on 4 main blocks:
• Automatic init engine: PCIe and NVMe device initialization, hardware discovering
• User Interface: memory configuration and input for the transfer request by the API
• NVMe command manager: translation of the data request from API into a NVMe command.
Submission and completion pointers management
• Data Transfer Engine: management of the data transfer between the NVMe SSD and the
FIFO/memory
It delivers very low latency since it is a full hardware host NVMe implementation. That takes only few
dozens of clock cycles (compared to multiple thousands of clock cycles for a software NVMe driver on a
CPU). In addition, there is no needs of PCIe interrupt management because it is directly processed by
the Host NVMe manager, therefore avoiding context switches.